Euromicro Conference on
Digital System Design

September 1 – 3, 2021
Virtual Event
Organized from Palermo | Italy

DSD 2021

DSD 2021 Call For Papers Committees Submissions Registration

Paper Submission Deadline:

1 April 2021 20 April 2021 5 May 2021

Notification of Acceptance:

15 May 2021 5 June 2021 12 June 2021

Camera-Ready Papers:

15 June 2021 20 June 2021 2 July 2021

Dependability, Testing and Fault Tolerance in Digital Systems (DTFT)

Special Session Scope

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from system specification down to micro-architectures, digital circuits and VLSI implementations.

Every designed system has to be tested several times during its life-time - during its design, production, and its in-field operation. The need for testing strictly depends on the actual use of the system, if the system can be repaired or not, and on the requirements for the system, e.g., if the system must be dependable, fault tolerant, etc. The design must reflect these requirements. The special session on "Dependability, Testing, and Fault Tolerance in Digital Systems" (DTFT) addresses emerging issues, hot problems, new solution methods and their hardware and software implementations in all fields of digital and analog/mixed-signal system dependability and testing. It is especially focused on testing, dependability, and fault-tolerance of SoC based designs and modern embedded applications.

Papers on any of the following and related topics can be submitted to the special session:

  • Diagnosis & testing of embedded systems, SoC and NoC testing
  • Memory and CPU testing
  • Analog, mixed-signal and RF, IDDQ and current testing
  • Built-In Self-Test: off-line BIST and on-line BIST, test compression methods
  • Testability analysis, design for testability
  • Error detection and correction, on-line testing, design of checkers
  • Design of dependable (robust) circuits and systems, error mitigation techniques
  • Defect/fault tolerant architectures (SoCs, NoCs, embedded systems)
  • FPGA based fault tolerant systems, partial/full reconfiguration based methods
  • Fault injection techniques, fault simulation/emulation
  • Dependability modeling, dependability analysis and validation
  • Formal approaches in fault tolerant systems design
  • System diagnosis
  • Dependable design in practical applications

Special Session Chairs

P. Fišer (CTU in Prague, CZ)

Z. Kotásek (BUT in Brno, CZ)

Special Session Program Committee

P. Bernardi, Politecnico di Torino (IT)

A. Bosio, Lyon Institute of Nanotechnology (FR)

L. Cassano, University of Pisa (IT)

G. Di Natale, TIMA, Grenoble (FR)

G. Fey, Hamburg Univ. of Technology (DE)

P. Fišer, CTU in Prague, CZ

T. Garbolino, Silesian TU, Gliwice (PL)

M. Jenihhin, TTU, Tallin (EE)

M. Keim, Mentor Graphics, Wilsonville (US)

Z. Kotásek, BUT, Brno (CZ)

H. Kubátová, CTU in Prague (CZ)

A. McEwan, University of Derby (UK)

L. Miclea, TU of Cluj-Napoca (RO)

A. Miele, Politecnico di Milano (IT)

A. Orailoglu, UC, San Diego (US)

R. Růžička, BUT, Brno (CZ)

T. Sato, Fukuoka University (JP)

M. Sonza Reorda, Politecnico di Torino (IT)

A. Steininger, Vienna U. of Techn. (AT)

V. Stopjaková, STU, Bratislava (SK)

R. Ubar, TTU, Tallinn (EE)